assembly: registers and flags
%eax | %ecx | %edx | %ebx | %esi | %edx
Temporary data, General purpose registers
%esp | %ebp
Current: stack top | stack frame
CF | ZF | SF | OF
Carry flag | Zero flag | Sign flag | Overflow flag
Note: flags are not set by lea instruction.
assembly: jumps and shifts
sal | sar
arithmetic shift left | right
shl | shr
logical shift left | right
jz | jnz
jump if == 0,"zero" | != 0,"not zero"
je | jne | jg | jge | jl | jle
jump if == | != | > | >= | < | <=
jump and store
jmp | jmp *reg
unconditional relative jump| absolute jump, reg is a registry.
ja | jb (unsigned)
jump above | below
assembly: compares and flags
cmp b, a
a - b
test b, a
a & b
zf "zero flag"
set when a&b== 0
sf "signed flag"
set when a&b < 0
assembly: getting setting
lea a, b
load effective address a into b
mov a, b
move contents of a into b
cmov (z,nz,e,ne,g,ge,l,le,ng,nge,nl,nle,a,b, ...)
compare and move if condition is met.
movl %edx, %eax
eax = edx, eax bendir á edx
movl (%edx), %eax
eax = *edx, eax verður bendir á innihald edx
movl %edx, (%eax)
*eax = edx, eax bendir á bendinn að innihaldi edx
movl (%edx), (%eax)
eax = edx, yfirskrifar innihald eax með innihaldi edx.
address(mn[i][j]) = 0+i*N+4j
address(nm[i][j]) = 0+i*M+4j
Given the arrays:
int mn[M][N]; and int nm[N][M];
Reading a disk sector(sequence)
1: CPU initiates disk read, writes cmd, lbn and desk to a DC port(address)
2: DC reads sector and performs a DMA transfer into main memory
3: DC notifies CPU with interrupt signal when DMA transfer completes
DC: Disk controller
DMA: direct memory access
lbn: logical block number
Memory system parameters
Number of addresses in virtual address space
Number of addresses in physical address space
Components of PA(physical address)
Physical page offset(same as VPO)
Physical page number.
Byte offset within cache line
Components of VA(Virtual Address)
Virtual page offset
Virtual page number
> Recently referenced items are likely to be referenced again in the near future.
> Items with nearby addresses tend to be referenced close together in time.
Simple Memory System Cache
holds recently used PTE's, located on the cpu chip.
Page table entry, physical address of data in cache/memory
Child stoppd or killd