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STY 2013 Final Cheat Sheet by [deleted]

STY 2013 Final
array     assembly     sty     registers     flags     cache     jumps     shifts     signals     memnory

assembly: registers and flags

%eax | %ecx | %edx | %ebx | %esi | %edx
Temporary data, General purpose registers
%esp | %ebp
Current: stack top | stack frame
%eip
Instru­ction pointer
CF | ZF | SF | OF
Carry flag | Zero flag | Sign flag | Overflow flag
Note: flags are not set by lea instru­ction.

assembly: jumps and shifts

sal | sar
arithmetic shift left | right
shl | shr
logical shift left | right
jz | jnz
jump if == 0,"z­ero­" | != 0,"not zero"
je | jne | jg | jge | jl | jle
jump if == | != | > | >= | < | <=
js
jump and store
jmp | jmp *reg
uncond­itional relative jump| absolute jump, reg is a registry.
ja | jb (unsigned)
jump above | below

assembly: compares and flags

cmp b, a
a - b
test b, a
a & b
zf "zero flag"
set when a&b== 0
sf "­signed flag"
set when a&b < 0

assembly: getting setting

lea a, b
load effective address a into b
mov a, b
move contents of a into b
cmov (z,nz,­e,n­e,g­,ge­,l,­le,­ng,­nge­,nl­,nl­e,a,b, ...)
compare and move if condition is met.
movl %edx, %eax
eax = edx, eax bendir á edx
movl (%edx), %eax
eax = *edx, eax verður bendir á innihald edx
movl %edx, (%eax)
*eax = edx, eax bendir á bendinn að innihaldi edx
movl (%edx), (%eax)
eax = edx, yfirsk­rifar innihald eax með innihaldi edx.
 

Array shizznit

addres­s(m­n[i­][j]) = 0+i*N+4j
addres­s(n­m[i­][j]) = 0+i*M+4j
Given the arrays:
int mn[M][N]; and int nm[N][M];

Reading a disk sector­(se­quence)

1: CPU initiates disk read, writes cmd, lbn and desk to a DC port(a­ddress)
2: DC reads sector and performs a DMA transfer into main memory
3: DC notifies CPU with inter­rupt signal when DMA transfer completes
DC: Disk controller
DMA: direct memory access
cmd: command
lbn: logical block number
dest: destin­ation

Memory system parameters

N=2n
Number of addresses in virtual address space
M=2m
Number of addresses in physical address space
P=2p
Page size(b­ytes)

Components of PA(phy­sical address)

PPO
Physical page offset­(same as VPO)
PPN
Physical page number.
CO
Byte offset within cache line
CI
Cache index
CT
Cache tag

Components of VA(Virtual Address)

TLBI
TLB index
TLBT
TLB tag
VPO
Virtual page offset
VPN
Virtual page number

Locality

Temporal locali­ty:
> Recently referenced items are likely to be referenced again in the near future.
Spatial locali­ty:
> Items with nearby addresses tend to be referenced close together in time.
 

Memory Hierarchy

Simple Memory System TLB

Simple Memory System Cache

Cache

TLB
holds recently used PTE's, located on the cpu chip.
PTE
Page table entry, physical address of data in cache/­memory

Signals

ID
Name
Default Action
Event
2
SIGINT
Terminate
Interu­pt,­ctrl-c
9
SIGKILL
Terminate
Kill (unavo­idable)
11
SIGSEGV
Termin­ate­&Dump
Segfault
14
SIGALRM
Terminate
Timer signal
15
SIGTERM
Terminate
Kill nicely­(ca­tch­able)
17
SIGCHLD
Ignore
Child stoppd or killd

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