Byte ordering of 0x01234567
Byte representation of ints
Bit operations (integral data type)
Converting 2's C to decimal
Normalized encoding example
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SetX dest: only set lower 1 byte of register
one operand instructions
useful instruction for division
Implicitly setting condition code: addq src, dest
Bad cases for conditional move
Effect of operations
Logical Operations |
CF=0, OF=0 |
shift |
CF=value of last bit shifted out; OF=0 |
INC, DEC |
OF and ZF may change, CF unchanged |
Explicitly setting condition codes
cmpl b, a |
a-b result not stored anywhere |
testq b, a |
a&b result not stored anywhere |
When are local variables in stack?
Enough registers |
No reference to & so no need to go to memory |
No arrays, structures |
Structure representation
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Cache miss
3 cases |
compulsory, capacity, conflict |
How to reduce miss |
block size++, associativity++, cache size++ |
Reducing miss penalty |
write through (update all) vs write back (update when needed) |
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multilevel cache (optimize hit rate L1, miss rate L2) |
Replacement policies |
LRU, LFU, FIFO, rand |
Why VM
memory management and protection |
permission bits; uses main efficiently(send unneeded to disk) |
Process isolation/memory protection |
own add spaces; can't interfere with another's memory |
loading linking simplified |
VP partitioned to 3 subsets
Unallocated |
not yet created, no data, no space |
Uncached/cached |
currently cached/not cached |
Address translation w page table
Speed: TLB hit, mem access-1
TLB miss (rare with high assoc): 3 mem accesses
size-- multilevel page table
cache and VM
cache uses PA, since with VA, although can be accessed asap, aliasing, 2 VA may map to same block, would not know which one |
mem alloc challenges
memory utilization (sum of malloc'd data/heap size) |
good performance (malloc/free calls return quick) |
constraints: can't modify malloc'd memory; can't move malloc'd block |
implicit free list with footer and header
explicit free list (pointer don't space+)
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